Duration: 3-5 full days
Format: in-house and online training
The training provides an understanding of the Jacinto 7 Multicore Processor Architecture from the Boot Process to the system in operation. You learn how to boot the multicore SoC and how to use Inter-Processor communication and synchronization mechanism. The training makes sure that attendees can benefit from their knowledge when working with integrated MCUs running RTOS or Baremetal as well as with Linux on ARM Cortex A72 Cores.
We will start with setting up the environment to compile code for both Embedded Linux OS running on Arm Cortex A72 and RTOS/Baremetal on integrated R5F MCUs or DSPs. Part 2 highlights the boot flow of the multicore SoC and how to create the necessary components from the bootloaders to the finished embedded Linux or RTOS programs.
The attendees will also learn how to use the available hardware features to synchronize and communicate between different cores. A deep dive into multicore programming and data movement is part of the training.
Compiling Linux Kernel and Yocto for Jacinto 7 is also part of the training.
Embedded C/C++ Experience
Knowledge in Embedded Processors
Understanding of Embedded Operating Systems – RTOS – Linux
Jacinto 7 Processor Overview
Software Development Kit Overview
Platform Development Kit
Lab 1.1: Getting Started with Jacinto 7 SDK / Development Environment under Linux/Windows
Lab 1.2: Compile SDK Examples
Lab 1.3: Prepare Linux SDK Development and Debug Environment (NFS/TFTP etc.)
Lab 2.1: Compile SDK Examples
Lab 2.2 CCS Projects /Debugging Tools
Lab 2.3 Compile using Make
Jacinto 7 Boot Flow
Different Possibilities to boot all available Cores on Jacinto7
Lab 3.1: Boot Flow Jacinto 7
Lab 3.2: Boot Flow Jacinto 7
Lab 3.3: Build Uboot (Optional)
Understand Inter Core Communication using shred memory / IPC
Deep Dive into IPC Implementation and how to use it.
Lab 4.1: How to use IPC for communication between MCU Domain and Main Domain Cores
Lab 4.2: Using Rpmessages to communicate between Cores running RTOS/Linux or Baremetal
Lab 4.3: Implement an IPC Example on ARM Cortex A72 running Linux
Lab 4.4: Boot the System with A72 running Linux and your own examples on the other cores.
Understand Memory Architecture and memory partitioning across multicore SoC.
Multicore Data movement mechanisms / DMA / HW Spinlock / Shared Memory etc.
Understand Security Concept
Understand Powem and Resource Management
Understanding Pinmuxing in a multicore environment
PMIC & power custom changes
Peripherals and Clock Configuration
DDR Memory Configuration
Linux/Uboot device tree
Lab 8.1: Peripheral Drivers / CSL Timer
Lab 8.2_RTOS: Peripheral Drivers / CSL HW Spinlock
Lab 8.2_Linux: HW Spinlock
Lab 8.3: Peripheral Drivers / CSL HW Mailbox
HW safety overview
Software safety overview
Understand 9G and 2G Switch Architecture and Software Support
Lab10. Ethernet Switch Configuration under Linux.
Compile Linux Kernel
Build Yocto Distribution
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